The present invention relates generally to processes for manufacturing insulated gate power semiconductor devices such as MOSFETs, as well as other more complex devices including MOSFET-like structures, such as Insulated Gate Rectifiers (IGRs), MOS-controlled thyristors and MOS-gated thyristors. The invention more particularly relates to processes for forming the upper electrode and base regions of such devices without any critically-aligned masking steps, thereby reducing the minimum cell size.
Known power MOSFETs generally comprise a multiplicity of individual unit cells (sometimes numbering in the thousands or tens of thousands) formed on a single silicon semiconductor wafer in the order of 300 mils (0.3 in.) square in size and electrically connected in parallel. Each cell is typically about twenty-five microns in width. A number of geometric arrangements for the unit cells are possible, including elongated strips.
One particular known process for manufacturing power MOSFETs is a double diffusion technique which begins with a common drain region of, for example, N conductivity type semiconductor material, in turn formed on an N+ conductivity type substrate. Within the drain region a base region is formed by means of a first diffusion to introduce impurities of one type, and then a source region is formed entirely within the base region by means of a second diffusion to introduce impurities of opposite type. If the drain region is N type, then the first diffusion is done with acceptor impurities to produce a P type base region, and the second diffusion is done with donor impurities to produce an N+ type source region. At the drain region surface, the base region exists as a band between said source and drain regions.
Conductive gate electrodes are formed on the surface over the base region band and separated by a gate insulating layer to define an insulated gate electrode structure. Typically, the gate electrodes are formed of highly-doped polysilicon. When voltage of proper polarity is applied to the gate electrodes during operation, an electric field extends through the gate insulating layer into the base region inducing a conductive channel just under the surface. Current flows horizontally between the source and drain region through the conductive channel.
To form the insulated gate electrode structure, during initial wafer preparation a uniform gate insulating oxide layer and then a uniform layer of highly-doped polysilicon are grown over the drain region, prior to any introduction of impurities to form the base and source regions. Channels are then etched through the polysilicon layer and the gate insulating oxide to define the polysilicon gate electrode structures spaced along the drain region.
In a power MOSFET structure, the source, base and drain regions correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. As is known, if this parasitic bipolar transistor is allowed to turn on during operation of the power MOSFET, the blocking voltage and the dV/dt rating of the power MOSFET are substantially degraded. Accordingly, in order to prevent the turn on of the parasitic bipolar transistor during operation of the power MOSFET, the layers comprising the source and base regions are normally shorted together by means of an ohmic connection.
This same general MOSFET structure can be included in other, more complex devices. For example, rather than an N+ conductivity type substrate, a P+ conductivity type substrate may be employed, which becomes the anode region of an Insulated Gate or a MOS gated thyristor (MGT) depending on the density of shorts. The previous N conductivity-type drain region is formed as before, but is more generally termed herein a "first region", while the P+ conductivity type anode is herein termed a "second region". The P conductivity-type base region is formed as before in the first region, and the N+ conductivity-type region is formed in the base region. In the case of an IGR, this latter N+ conductivity type region is not termed a source region as before, but rather is a rectifier cathode region or, more generally, an upper electrode region.
As another example, a third device region, of N+ conductivity type, may be provided below a P (instead of P+) second region to form the lower main electrode region of an MOS-controlled thyristor.
In all of these cases, it will be appreciated that the MOS gate structure is essentially identical, and that the only substantial variations in the overall device structure are in the layers below the first region. In all cases, a short between the upper electrode region (whether is is termed a MOSFET source, an IGR cathode, or a MOS-gated thyristor main electrode region) and the base region is desired. In all cases, device metallization terminals are connected to the device upper electrode region and the gate electrodes.
For convenience, the invention is described herein primarily in the context of a MOSFET. However, it will be appreciated in view of the foregoing that the invention is equally applicable to various other insulated-gate semiconductor devices.
Known power MOSFET designs in manufacture typically require five to seven masking steps, some of which must be aligned to each other with high accuracy to produce working devices. In particular, to form the source-base short, between the first and second diffusion steps a diffusion barrier is applied by means of selective masking over a portion of the base diffusion surface area to prevent the subsequent source diffusion from entering the base diffusion in the selectively masked area. Thus a shorting extension of the base region extends to the surface. Thereafter, the selective mask is removed, and metallization is applied for the source electrode. A portion of the source metallization also makes ohmic contact with the previously masked area of the base region.
The large number of masking steps and need for alignment in the prior art processes decrease the process yield. Further, due to the need to provide tolerance for misalignment, unit cell size is larger than would otherwise be needed, undesirably increasing spreading resistance effects. Additionally, prior art process generally provide encased gate electrode structures having remote gate electrode contacts, thus increasing the gate input impedance.
In the above-incorporated commonly-assigned Temple application Ser. No. 406,731, various processes are disclosed for manufacturing power MOSFETs and similar devices. These processes are characterized by involving a minimal number of photolithographic masking steps and being fail-safe in a number of respects. In the processes disclosed in the above-identified Temple application Ser. No. 406,731, polysilicon gate MOSFETs are manufactured beginning with a semiconductor wafer including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. Through subsequent masking and etching steps, channels are etched through the polysilicon gate layer and then on through the gate insulating layer to the drain region. In general, the processes of Ser. No. 406,731 employ a single undercut etch step which leaves an overhanging layer over the polysilicon gate electrodes. The unetched portions define polysilicon gate electrode structures spaced along the drain region. Employing these polysilicon gate electrode structures as masks, impurities are introduced into the drain region through the surface between the gate electrodes, and then driven by thermal diffusion to form appropriately located base and source regions. The source region is located both laterally and vertically within the base region. In accordance with various specific processes therein disclosed, these base and source impurities are introduced either by ion implantation, or from a gas source, or a combination of the two. In the case of ion implantation, the impurities in some process variations are introduced through the gate insulating layer. A number of process alternatives are disclosed for forming a shorting extension of the base region up through and to a portion of the surface of the source region. Many of these process alternatives employ the overhang left by the undercut etch to form such shorting extension in the source region surface portion and therefore are self-masked. Two general MOSFET structures are formed in accordance with the processes disclosed in application Ser. No. 406,731. One structure has metallized gate terminal fingers, and is formed employing one-mask processes. The other structure has gate fingers encased in insulating oxide and connected to remote gate contacts, and is formed employing the three-mask processes. The preferred processes for both structures require selective oxidation of the polysilicon gate electrode material, and various approaches to this selective oxidation are described.
In the other above-incorporated patent application, Temple application Ser. No. 406,738, various process alternatives are disclosed, characterized generally by employing a two-step etch process to form the source-to-base short, without any requirement for an undercut etch leaving an overhang for self-masking. (However, for automatic separation of source and gate metallization, an overhanging layer of a conductive refractory material is beneficial.)
In brief, the process alternative of Ser. No. 406,738 employs the following sequence for forming the source-to-base short: (1) Following initial wafer preparation, a narrow etch at least to the gate insulator layer to form a narrow channel. (2) Form a defined short region employing the sides of the narrow channel as masks. (3) A lateral etch to widen channel. (4) Form source and base regions.
The present invention provides an alternative two-step etch process for forming the source-to-base short. In general, the present invention provides a self-aligned techniques wherein a mask formed between the first and second etch steps serves as a combined selective oxidation and diffusion mask.